1. Field of the Invention
This invention relates to the field of memory circuits. More particularly, this invention relates to memory circuits using bit lines precharged to a precharged state prior to a memory access operation to a memory cell via one or more respective precharged bit line.
2. Description of the Prior Art
It is known to provide memory circuits, such as RAM circuits, cache memory circuits and the like, which utilize arrays of memory cells arranged in rows and columns. Pairs of bit lines pass between respective memory cells within a column of memory cells. A row select signal is used subsequent to an address decoding to select a row of memory cells within the array to be coupled to their respective bit line pairs. (It may be that only a subset of the memory cells within a row are actually read in a given operation, e.g. a particular word within a multi-word row may be required for access). Depending upon the data value stored within a memory cell the bit line pair coupled to that memory cell when the memory cell is being read will have one of its bit lines discharged from a precharged state down towards the ground voltage. A sense amplifier coupled to the bit lines being read will sense a low voltage level from a partial discharged one of the two bit lines of the bit line pair and determine from this whether a 0 or a 1 was stored in the memory cell. The bit line being discharged will typically not be completely discharged since the sense amplifier will detect the difference in voltage when it is only partially discharged.
Subsequent to the read operation, the discharged bit lines need to be precharged back up to their precharged state. A precharge circuit operable subsequent to the read serves to return the partially discharged bit lines back to the precharged state.
It will be appreciated that when an entire row of memory cells is selected by the address decoder, all of these will be coupled to their respective bit line pairs and cause their own bit line discharge to occur. It may be that only some of these memory cells actually require to be read, e.g. only a single word or word pair is being read from a multiple word memory row. Nevertheless, all of the bit lines for that memory row need to be precharged back up to the precharged state.
During a write operation to a memory cell, the bit line pair is used with one of the bit lines being driven high and the other being driven low so as to force a particular data value to be stored within a memory cell coupled to that bit line by a current row select signal. Contrasting with a read operation, a write operation does typically force one of the bit lines of a bit line pair fully down to a ground voltage level with the other at the full rail voltage so as to overcome the xe2x80x9cstickinessxe2x80x9d of the memory cell being written to. A result of this is that the fully discharged bit line which has been grounded needs to be recharged all the way back to its precharge level. Thus, the pre-charging subsequent to a write operation can consume a disadvantageous amount of time.
It will be appreciated that memory performance either or both in terms of memory access speed and memory cycle time is a critical performance parameter within data processing systems. Measures which can increase such memory performance are strongly advantageous. The time within the memory cycle needed to precharge the bit lines following a memory access operation represents a significant proportion of the total memory cycle time and accordingly measures which can speed the pre-charging are advantageous. The time taken to turn off the bit line prechargers can also influence the memory access time if this time to turn off the prechargers is longer than the time taken to assert a row line during a parallel row decoding operation.
One approach to speeding pre-charging is to utilize pre-charging circuits containing stronger transistors capable of delivering more pre-charging current and so raising the bit lines to the precharged state more quickly. However, a disadvantage of this approach is that such stronger pre-charging circuits will tend to consume a disadvantageous amount of circuit area and may not be pitch matched to the other circuit elements within the memory. Furthermore, the control of such stronger pre-charging circuits will tend to be slower negating at least some of the speed advantage associated with the stronger pre-charging circuits and will also consume more power.
Viewed from one aspect the present invention provides a memory circuit comprising:
a plurality of memory cells operable to store respective data values;
a plurality of bit lines coupled to said plurality of memory cells and operable such that when a target memory cell is subject to a memory access operation a target bit line coupled to said target memory cell is driven away from a precharged state;
a precharge circuit operable to perform a precharge operation to precharge said plurality of bit lines to said precharged state prior to said memory access operation; and
a charge sharing circuit operable following said memory access to couple bit lines of one or more memory cells not subject to said memory access operation to said target bit line that was driven away from said precharged state to share charge with is said target bit line to augment said precharge circuit in returning said target bit line to said precharged state.
The invention recognizes that within a memory circuit undergoing a memory access operation some of the bit lines will not be used in that memory access operation and the hold a significant amount of charge and have associated pre-charging circuits. Accordingly, the precharging operation can be advantageously speeded by sharing charge between bit lines which have not been subject to the memory access operation and those which have been driven away from the precharged state. The capacitance of the unused bit lines acts as a charge store which is then shared with the partially discharged bit lines which have been subject to a memory access. The precharging circuits associated with the bit lines which are sharing their charge can also then all act together to restore the precharged state more rapidly. This allows an advantageous decrease in memory cycle time.
In preferred embodiments of the invention the charge sharing circuit comprises one or more switching circuits operable during said memory access operation to selectively couple said target bit line to an output of said memory circuit and operable during said precharge operation to couple said target bit line to said bit lines of one or more memory cells not subject to said memory access operation.
In accordance with the above feature circuit elements which are already included within the memory circuit for normal memory access to select a the particular bit line pair to be connected to the memory output can be reused for the charge sharing operation by controlling them in a different way such that bit lines which are to share charge are coupled together. This reduces the circuit overhead associated with the charge sharing technique.
It will be appreciated that one form of memory access operation which may utilize the current technique is a write operation in which the target bit line is driven away from the precharged state by a write driver circuit so as to force a data value into the target memory cell. As previously mentioned, write operations tend to require a greater degree of precharging subsequent to those operations and accordingly can contribute significantly to the limiting case which must be dealt with within the memory cycle time.
Another possibility is that the memory access operation is a read operation in which the target bit line is driven away from the precharged state in dependence upon the data value stored within the target memory cell. Whilst during a read operation the bit lines are discharged less deeply, the present technique is still highly useful in that a large number of read operations take place and in many of these an entire memory row will have been at least partially discharged and require precharging even though only a portion of the memory cells within that memory row are required for the read.
In particularly preferred embodiments of the invention the memory is arranged into two or more memory banks such that whilst one memory bank is being accessed at least one other memory bank is not being accessed. Thus, the non-access memory bank will not be subject to any discharge of its bit lines and so may charge share with the bit lines of the accessed memory bank so as to speed up the precharge operation.
Whilst it is not essential to the general aspect of the invention that the memory should be arranged in rows and columns, the invention is well suited to such arrangements as the bit line charge sharing may be advantageously readily provided within such regular architectures.
It will be appreciated that the invention is applicable to a wide type of different memories and is not limited to RAM memories, cache memories or any other type of memory. The technique is also not limited to any polarity of charging and discharging or any particular charge level in the precharged state.
Viewed from another aspect the present invention provides a method of to operating a memory circuit, said method comprising the steps of:
storing data values within respective ones of a plurality of memory cells, said plurality of memory cells being coupled to a plurality of bit lines;
when a target memory cell is subject to a memory access operation, driving a target bit line coupled to said target memory cell away from a precharged state;
performing a precharge operation to precharge said plurality of bit lines to said precharged state prior to said memory access operation; and
following said memory access, coupling bit lines of one or more memory cells not subject to said memory access operation to said target bit line that was driven away from said precharged state to share charge with said target bit line to assist in said precharge operation returning said target bit line to said precharged state.
The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings.